DDR5 is showing increased resistance to Rowhammer attacks compared to previous generations. The minimum hammer count (HCmin) is a metric to...
This paper presents REFault, a novel and timely fault injection platform designed to address a critical gap in Rowhammer research on DDR5 memory. The...
The density of memory cells in modern DRAM is so high that frequently accessing a memory row can flip bits in nearby rows. That effect is c...
This paper, titled "Flipper: Rowhammer on Steroids," presents a compelling advancement in Rowhammer research by introducing Flipper, an amplification...
In many real-world scenarios, being able to infer specific software versions or variations of cryptographic libraries is critical to mounti...
This paper, titled "PortPrint: Identifying Inaccessible Code with Port Contention," addresses a critical challenge in security research: inferring spe...
Microarchitectural attacks threaten system security and privacy, especially if they can be mounted without native code execution. Recent re...
This paper introduces a significant new vector for microarchitectural attacks, expanding the landscape of "scriptless" side-channel vulnerabilities. B...
Detecting malicious software or hardware behavior during the operation of a computer system requires observables from one or more abstracti...
The submission, titled "Poster: A microarchitectural signals analysis platform to craft Hardware Security Counters," addresses a critical challenge in...
This poster proposes to address the critical challenge of "Isolating PIM from OS Level Adversaries," a topic of high relevance in contemporary system...
To protect cryptographic implementations from side-channel vulnerabilities, developers must adopt constant-time programming practices. As...
This poster addresses a critical gap in the field of cryptographic security: the persistent presence of side-channel vulnerabilities despite the avail...
This talk overviews our recent work on TLBlur, a novel approach that leverages compiler instrumentation and the recent AEX-Notify hardware...
This talk outlines "TLBlur," a promising new approach to mitigating controlled-channel attacks against Intel SGX enclaves. The work leverages a novel...
CHERI (Capability Hardware Enhanced RISC Instructions) is a capability-based ISA extension providing spatial memory protection and compar...
The abstract for "Talk: Transient-execution attacks on the CHERI Morello platform" introduces a highly timely and critical area of research at the int...
I am unable to provide a review at this time as the abstract text has not been provided. The abstract is a crucial component for evaluating a manuscri...
Showing 7191 to 7200 of 13123 results
By Sciaria
By Sciaria
By Sciaria
By Sciaria
By Sciaria
By Sciaria